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Jie LEI

Research Fellow | University of Technology Sydney

🚀 Pioneering LLM-Aided FPGA Design

I specialize in deploying algorithms on FPGAs more efficiently through cutting-edge LLM-aided hardware design methodologies, achieving breakthrough performance improvements in algorithm-hardware co-design.

🏆 Key Achievements

  • 157× error reduction through self-learning LLM-driven FPGA optimization
  • 360 MHz timing closure on complex signal processing systems
  • Complete algorithm-to-FPGA ecosystem: MATLAB2HLS, Python2HLS, CPP2FPGA frameworks
  • 8×8 MIMO-OFDM receiver at 200 MHz with 1.5 Gbps throughput
  • Multi-agent AI framework with 8 specialized agents for automated hardware design

🔬 Research Impact

My work bridges the gap between artificial intelligence and hardware acceleration, making complex algorithms more accessible through efficient FPGA implementation.

Current Research Areas

  • 🤖 LLM-Aided Hardware Design: Pioneering AI-assisted FPGA development workflows
  • 📡 5G/6G Signal Processing: Real-time wireless communication system implementation
  • 🛰️ Space-Grade Systems: CCSDS standard implementations for satellite applications
  • ⚡ High Level Synthesis: MATLAB to HLS automation with AI optimization
  • 🎯 Algorithm-Hardware Co-design: Bridging software and hardware domains

🌟 Research Highlights

Open Source Contributions

  • 35+ active repositories on GitHub with 110+ total stars
  • MATLAB2HLS v13: Self-learning framework with 24+ case studies
  • Python2HLS: NumPy/SciPy to HLS with 87% latency reduction
  • CPP2FPGA: JPEG-LS compression with 6-phase transformation pipeline
  • RX_AP_UE: 8×8 MIMO-OFDM receiver at 1.5 Gbps

Real-World Deployments

  • Complete USRP X310 pipeline for live 5G NR signal detection
  • 8×8 MIMO wireless receiver with Cholesky-based equalization
  • Space-grade hyperspectral compression (CCSDS 123.0-B-1) with 41.7% resource reduction

🎓 Academic Excellence

PhD from Xidian University 15+ years academic experience UCLA Visiting Scholar

Progressed from Associate Professor to Professor at Xidian University before joining UTS as Research Fellow, bringing deep expertise in signal processing and hardware implementation.

📬 Connect

“Making complex algorithms accessible through efficient hardware implementation while pioneering the integration of AI and FPGA design.”