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Jie LEI

Research Fellow | University of Technology Sydney

🚀 Pioneering LLM-Aided FPGA Design

I specialize in deploying algorithms on FPGAs more efficiently through cutting-edge LLM-aided hardware design methodologies, achieving breakthrough performance improvements in algorithm-hardware co-design.

🏆 Key Achievements

  • 18x latency improvements through LLM-assisted FPGA optimization
  • 250 MHz timing closure breakthroughs on complex signal processing systems
  • Complete 5G NR deployment pipeline from MATLAB to live USRP hardware
  • Multi-agent AI framework pioneering automated hardware design workflows

🔬 Research Impact

My work bridges the gap between artificial intelligence and hardware acceleration, making complex algorithms more accessible through efficient FPGA implementation.

Current Research Areas

  • 🤖 LLM-Aided Hardware Design: Pioneering AI-assisted FPGA development workflows
  • 📡 5G/6G Signal Processing: Real-time wireless communication system implementation
  • 🛰️ Space-Grade Systems: CCSDS standard implementations for satellite applications
  • ⚡ High Level Synthesis: MATLAB to HLS automation with AI optimization
  • 🎯 Algorithm-Hardware Co-design: Bridging software and hardware domains

🌟 Research Highlights

Open Source Contributions

  • 6+ active repositories on GitHub with 80+ total stars
  • peakPicker: First quantitative LLM-FPGA comparison study
  • llm-fpga-design: Multi-agent framework for automated FPGA development
  • pulseDetector: Revolutionary LLM-aided signal processing implementation

Real-World Deployments

  • Complete USRP X310 pipeline for live 5G NR signal detection
  • 2x2 MIMO testbed for environmental sensing applications
  • Space-grade hyperspectral compression with 41.7% resource reduction

🎓 Academic Excellence

PhD from Xidian University 15+ years academic experience UCLA Visiting Scholar

Progressed from Associate Professor to Professor at Xidian University before joining UTS as Research Fellow, bringing deep expertise in signal processing and hardware implementation.

📬 Connect

“Making complex algorithms accessible through efficient hardware implementation while pioneering the integration of AI and FPGA design.”