Jie Lei

About

I am a Research Fellow at the University of Technology Sydney, working on algorithm-to-hardware design automation: methods and tools that take an algorithm and produce efficient, verified FPGA hardware. My current focus is pairing large language models with a strict, layer-by-layer verification discipline, so generated hardware can be trusted rather than merely assumed correct.

Before UTS I spent more than a decade at Xidian University in China, where my research centred on signal processing, hyperspectral image analysis, and hardware-accelerated implementation. I work across the full path from a mathematical specification to a circuit running on real silicon.

Experience

Research Fellow - University of Technology Sydney, Australia (Dec 2023 - present) Algorithm-to-hardware design automation, AI-assisted FPGA design, and wireless and signal-processing systems on software-defined radio.

Professor - Xidian University, China (2020 - 2023) Led research in algorithm-hardware co-design and FPGA prototyping for remote sensing and edge computing.

Associate Professor - Xidian University, China (2010 - 2020) Hyperspectral image processing and its FPGA implementation for satellite and airborne systems.

Visiting Scholar - University of California, Los Angeles, USA (2014 - 2016) Research with Prof. Jason Cong on high-throughput FPGA accelerators using high-level synthesis.

Education

PhD, Signal and Information Processing - Xidian University (2006 - 2010)

MEng, Telecommunication and Information Systems - Xidian University (2003 - 2006)

BEng, Electronic and Information Engineering - Xidian University (1999 - 2003)

Elsewhere