Work
Designs built with Python2Verilog, across error correction, signal processing and wireless systems, from single cores to complete physical layers. Everything below was generated and verified with the same AI-assisted method: a design is built as a math reference, then a hardware-timed model, then the circuit, and each layer is machine-checked against the one above it, so correctness rests on evidence rather than assumption. These are described in plain terms, as methods and capabilities rather than benchmark figures.
Python2Verilog, the framework
The evidence-governed flow behind every design on this page. It takes an executable algorithm through a math reference, a hardware-timed model, the circuit, implementation and board deployment, with a gate at every step. AI proposes candidates; standard tools execute them; independent checks decide acceptance, and those checks are themselves proven to catch planted faults before their verdicts count. Accepted designs become reusable families, and the output ships as modular kits, from portable RTL through board bring-up, embedded Linux and interconnect up to a working application.
Quantum error-correction decoder
The real-time classical decoder a fault-tolerant quantum computer cannot run without, rebuilt from first principles for IBM's gross code and generated from a model checked against the mathematics at every step. The work traced where such a decoder's speed limit comes from - the wiring of the code's graph rather than its logic - which makes the useful lever algorithmic: stop a stuck decoding attempt early.
802.11a Wi-Fi receiver
A complete Wi-Fi receiver, generated without anyone hand-writing the hardware, that decodes standard signals end to end and runs on a pocket-sized, USB-powered radio. Fed a standard waveform from MATLAB's own toolbox, it recovers the transmitted image bit-for-bit across every supported modulation.
5G error-correction decoder
The forward-error-correction engine at the heart of a 5G base station, generated across a wide range of code configurations, each matching the standard's reference exactly. Timing work on the flagship configuration shows how to close a deep, wiring-dominated decoder pipeline: find where the delay really sits, then cut it with registers placed where they help.
Deep-space decoder
An error-correction decoder for the codes that protect deep-space and satellite links, where a signal must survive extreme noise. One design covers every code size and rate of the standard, switching between them on the fly. It is validated on real silicon and sold as a licensed core with its own datasheet and user guide.
Wi-Fi transceiver on a custom RFSoC board
A complete Wi-Fi transmitter, receiver and link layer, running three generations of the standard from a single design that switches between them at runtime, with LDPC error-correction coding. On a custom radio board, with Linux on the chip's processors driving it, it carries live video over a real radio link.
4G base-station physical layer
The full physical layer of an LTE base station, both directions: random access, uplink data and control, turbo decoding and the downlink signal chain, serving many users from one shared datapath. It is checked against a MATLAB reference end to end, closed as a single implementation on one RFSoC chip, and its turbo decoder runs on real silicon.
Streaming spectral engine
A fast Fourier transform core, the spectral heart of OFDM radios such as Wi-Fi and 5G. It streams one sample per clock without stalling and adapts cleanly to different transform sizes.
Digital filter library
A family of configurable filters for conditioning radio signals, from simple anti-aliasing filters to multi-stage rate-changing chains. The generator leans on the FPGA's dedicated arithmetic blocks to keep every design lean.
Convolutional decoder
A maximum-likelihood decoder for the codes used in nearly every wireless standard, from Wi-Fi to satellite links. Folding the decoder trades logic against throughput while holding the clock, giving a menu of size-versus-speed points; a compact version runs inside the Wi-Fi receiver above, every mode bit-exact.
For the formal designs, validation, and measured results, see my publications and open-source repositories.