About
About Jie LEI
I am a Research Fellow at the University of Technology Sydney, pioneering the integration of Large Language Models (LLMs) with FPGA design workflows to achieve breakthrough performance improvements in algorithm-hardware co-design.
Research Philosophy
My work bridges the gap between artificial intelligence and hardware acceleration, fundamentally transforming how we approach FPGA development. I believe that the convergence of AI-assisted design tools with specialized hardware accelerators represents the future of computing, enabling complex algorithms to achieve optimal performance and energy efficiency that was previously unattainable.
🏆 Breakthrough Achievements
- 18x latency improvements through LLM-assisted FPGA optimization
- 96% LUT reduction (7,148 → 284 LUTs) in 5G NR signal processing
- 250 MHz timing closure breakthrough on Xilinx Kintex-7 platforms
- 60-70% development time reduction with multi-agent AI frameworks
- First quantitative LLM-FPGA comparison study published open-source
Expertise Areas
🤖 LLM-Aided Hardware Design
Pioneering the integration of Large Language Models with FPGA development workflows, achieving unprecedented automation in algorithm-to-hardware translation with performance optimization.
⚡ Advanced FPGA Prototyping
Developing efficient FPGA implementations for complex algorithms, with focus on AI-guided optimization techniques that maximize performance while minimizing resource utilization.
🔄 Intelligent High Level Synthesis
Converting high-level algorithm descriptions (MATLAB, Java, C++) to optimized hardware implementations using LLM-enhanced HLS methodologies and automated design space exploration.
📡 5G/6G Communications Systems
Designing and implementing real-time signal processing algorithms for next-generation wireless systems, with complete deployment pipelines from simulation to live hardware (USRP, RFNoC).
🛰️ Space-Grade System Design
Hardware-accelerated algorithms for mission-critical applications, including CCSDS standard implementations with radiation-hardened design principles and stringent SWaP constraints.
Career Journey
With over a decade of academic experience, I have progressed from Associate Professor to Professor at Xidian University before joining UTS as a Research Fellow. My international experience includes a visiting scholar position at UCLA, which broadened my research perspective and collaborative network.
🌍 Research Impact & Innovation
My research fundamentally transforms how we approach hardware design by making complex algorithms more accessible through AI-assisted FPGA implementation. This work enables real-world applications that were previously computationally prohibitive, with measurable impact:
Open Source Contributions
- 80+ GitHub stars across 6+ active repositories
- Open methodologies enabling reproducible LLM-FPGA research
- Educational resources democratizing advanced hardware design
Real-World Deployments
- Live 5G NR systems with USRP X310 hardware integration
- Environmental sensing applications using 2x2 MIMO testbeds
- Space-grade implementations meeting stringent aerospace requirements
Industry Applications
- 5G/6G wireless communications with real-time processing capabilities
- Satellite systems with CCSDS standard compliance
- High-performance computing with specialized accelerators
- Computer vision on edge devices with optimal resource utilization
🔬 Current Research at UTS
At the University of Technology Sydney, I am leading groundbreaking research that bridges artificial intelligence and FPGA design automation, developing revolutionary methodologies that will define the next generation of algorithm-hardware co-design:
- Multi-agent AI frameworks for complete automation of hardware design workflows
- Cross-language algorithm translation (MATLAB, Java, C++ → FPGA)
- Real-time deployment pipelines from algorithm conception to live hardware
- Performance optimization methodologies achieving 18x improvements over traditional approaches